A PFSCL based configurable logic block

This paper proposes a configurable logic block (CLB) for the efficient circuit realization in positive feedback source coupled logic (PFSCL) style. The proposed CLB incorporates the advantageous features of the PFSCL style and triple-tail cell concept. The operation of the new CLB is explained and the realization of different circuits by configuring the block is discussed. The efficiency of the proposed circuit realizations is evaluated and compared with the existing counterparts in terms of gate count, power and delay. A maximum reduction of 71 % in gate count, 64 % in power and 42 % in delay is achieved in circuit realizations employing the proposed CLB.