A 7GS/s, 1.2 V. pseudo logic encoder based flash ADC using TIQ technique

Ultra wide band communication systems extensively rely on low resolution and Giga samples per second data converters. Moreover, technology scaling beyond 90 nm drastically complicates the design of the communication systems. With the increasing complexity in communication systems, greater demand for higher performance and more conversion speed while maintaining power consumption at a reasonable level drives research towards new architectural and topological paradigms. In this paper, a novel architecture implementation for the 4-bit flash ADC is proposed. The design is suitable for low power high-speed applications. The architecture utilizes Threshold Quantization technique (TIQ), the gate sizes are carefully selected so that the input and output rise- and fall-times are about equal. The TIQ technique has been utilized here in order to meet low power requirements and for better implementation in SoC applications. The circuit is designed in CMOS 90 nm technology. A new digital encoder network called the Pseudo- dynamic NMOS encoder is proposed to be used in the proposed TIQ based architecture of flash ADC. The Pseudo-dynamic NMOS encoder outperforms all of the existing encoding networks. The new encoding network offers high data conversion rate with a low power consumption.