DFAL based implementation of frequency divider-by-3

Power Dissipation being an important parameter of any electronic system´s performance is a major topic of interest for scads of researchers. Frequency divider, a basic building block in ample electronic systems, dissipates a very high power and consumes substantial amount of energy. In this paper a frequency divider-by-3 circuit is implemented using diode free adiabatic logic (DFAL), which surpasses the static CMOS logic based frequency divider-by-3 in terms of power dissipation and power delay product (PDP). The functionality of the implemented circuit is verified through TSPICE simulations in Tanner EDA simulator by using 0.18 micron TSMC technology parameters. For the performance measures, average power dissipation and PDP of the DFAL based divider-by-3 circuit is compared with its static CMOS counterpart. The simulation results of constant load capacitance analysis and constant input frequency analysis confirm the superiority of DFAL based frequency divider-by-3.