A high-k, metal gate vertical-slit FET for ultra-low power and high-speed applications

In this paper, we propose a novel Vertical-Slit Field Effect Transistor (VeSFET) with high-k gate dielectrics and metallic gates with different work function (Φ_m). The gate dielectric material and gate electrodes in traditional VeSFETs are replaced by high-k dielectrics and metals, respectively. We investigate the effect of these on the electrical characteristics of our proposed device. Various performance parameters such as Drain Induced Barrier Lowering (DIBL), Sub-threshold Swing (SS), Threshold Voltage (VT), leakage power (P_off), propagation delay, I_on/I_off ratio are obtained using exhaustive TCAD simulations and compared with that of conventional VeSFETs. Our analysis shows that the proposed high-k metal gate VeSFET exhibits higher I_on/I_off ratio, lower leakage current, lower leakage power, lower delay with near ideal SS and minimum DIBL. Also, our proposed device exhibits higher on-current. This makes it a potential candidate for ultra-low power, high-speed applications with reduced short channel effects. To illustrate the benefits of our proposed device, we design a complementary inverter using the proposed high-k metal VeSFETs. Our analysis clearly highlights the improvement in delay and power dissipation obtained using the proposed structure when compared to that using conventional VeSFETs.