Investigation of III?V compound semiconductor materials on analog performance of Nanoscale RingFET

In present work, the impact of channel material engineering and gate oxide engineering on the RingFET architecture has been investigated for the first time. This investigation involves the study of various electrical parameters like drive current (I_d-V_gs), threshold voltage (V_th), Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), I_ON/I_OFF, and transconductance generation efficiency (g_m/I_d), under different device specifications. Furthermore investigation reveals the performance of III-V group semiconductor devices on RingFET for analog and digital application. Apart from these reliability issues the excessive gate leakage current has also been addressed.