An efficient approach to design a compact reversible programmable logic array

Reversibility of logic module has eminent application in low power CMOS design, quantum computing, nanotechnology and optical computing. On the other hand, configurability of PLDs (Programmable Logic Devices) reduces NRE (Nonrecurring engineering) cost and makes faster design process that offers customer a wide range of logic capacity, features, speed and voltage characteristics. In this paper, we propose a design methodology of RPLA (Reversible Programmable Logic Array) which reduces number of reversible gates, garbage outputs, quantum cost and constant inputs. An algorithm has been proposed for the construction of AND Plane and OR Plane of the RPLA. Comparative results show that the proposed design outperforms the existing designs in terms of numbers of gates, garbage outputs, quantum cost and constant inputs.