Tunnel transistors with circuit co-design in designing reliable logic gates for energy efficient computing

Tunnel FETs have attracted much attention recently for energy efficient designs. This paper presents design, analysis and benchmarking of Tunnel FET (TFET) based reliable XOR logic gates with circuit co-design for energy efficient computing at scaled supply voltages (0.1-0.3V). A specific variant of TFET ie., homo-junction TFET (where source and drain are doped with same material InGaAs) has been explored and at the circuit level three XOR gate topologies such as 12T, 8T and 6T have been proposed. For benchmarking, 20nm double-gate FinFET technology has been used for all the designs. In FinFET designs, it has been demonstrated that 12T design is more robust and reliable (in terms of full swing) and less energy efficient and 6T design is most energy efficient, but reduced reliability. We demonstrate that TFET´s´ steep slope characteristics enable the 12T design to be energy efficient option along with improved reliability and 6T design is the best in terms of energy efficiency and reliability amongst all designs at 0.1V V_DD.