• DocumentCode
    3767738
  • Title

    Design and analysis of 8 bit fully segmented digital to analog converter

  • Author

    Arpit Kumar Baranwal; Anurag;Balwinder Singh

  • Author_Institution
    ACSD, Centre for Development of Advanced Computing, Mohali, Punjab 160071, India
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper presents design of an 8-bit 1.8V fully segmented digital to analog converter (DAC) using 180nm CMOS technology. DAC is an essential part of digital signal processor. Digital to analog converter is employed in processing of digital signals and providing analog output in the form of current or voltage for corresponding binary input. The differential non linearity of a DAC shows variation in output corresponding to 1LSB change at input that is accuracy of data conversion. To achieve low non linearity or more accurate data conversion a DAC is designed with unary coding or a fully segmented digital to analog converter with current steering technique. The INL and DNL achieved in this research work are 0.145LSB and 0.013LSB respectively. The power consumption is simulated as 99.67mW.
  • Keywords
    "Decoding","Linearity","Digital-analog conversion","Logic gates","Encoding","Latches","Transistors"
  • Publisher
    ieee
  • Conference_Titel
    Recent Advances in Engineering & Computational Sciences (RAECS), 2015 2nd International Conference on
  • Type

    conf

  • DOI
    10.1109/RAECS.2015.7453307
  • Filename
    7453307