Area-efficient low PDP 8-bit vedic multiplier design using compressors

Multipliers perform the core operations in many complex systems such as arithmetic processors, image and digital signal processors. So, a performance optimized multiplier is a major design challenge. The partial product addition stage of the multiplier is the most time and power consuming stage. Thus, the key to enhance the overall performance of the multiplier is the improvement in the design of partial product addition stage. Using compressor adders, for partial product addition, the number of full adders and half adders are reduced resulting in significant reduction in area, delay and power consumption. In the present work, a novel higher-order compressor based 8-bit Vedic multiplier, is proposed. The designs are synthesized and analyzed using Cadence Encounter RTL Compiler in 180nm technology using nominal operating conditions. When compared with existing designs, the proposed multiplier shows substantial improvement in area, speed and Power Delay Product.