DocumentCode :
3768146
Title :
VLSI implementation of fast convolution
Author :
Pankaj Katkar;T N Sridhar;G M Sharath;S Sivanantham;K Sivasankaran
Author_Institution :
School of Electronics Engineering, VIT University, Vellore, India
fYear :
2015
Firstpage :
1
Lastpage :
5
Abstract :
Convolution is an algorithm widely used in image and video processing. Although its computation is simple, its implementation requires a high computational power and an intensive use of memory. This paper presents a direct method of reducing convolution processing time using hardware computing and implementations of discrete linear convolution of two finite length sequences. This implementation method is realized by simplifying the convolution building blocks.
Keywords :
"Convolution","Multiplexing","Shift registers","Clocks","Field programmable gate arrays","Hardware"
Publisher :
ieee
Conference_Titel :
Green Engineering and Technologies (IC-GET), 2015 Online International Conference on
Type :
conf
DOI :
10.1109/GET.2015.7453771
Filename :
7453771
Link To Document :
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