Design of low power DLL with TDC for jitter suppression

This project proposes a 90° phase-shift delay-locked loop (DLL) used in dynamic RAM for data sampling clock generation and clock synchronization. In previous DLL, the mismatch between the delay line segments which caused the process variation in the circuit. This proposed DLL reduce the process variation issues and also minimize the area by adopting a multiplying DLL based structure. The harmonic locking problem is prevented by a ring oscillator. The fine delay range selector and the resistance controlled fine delay unit is used to achieve a fast operating frequency with a finer resolution. It is fabricated using 180nm CMOS process and utilizes 1.1V supply voltage. The proposed DLL has an operating frequency ranging from 200MHz to 1GHz and consumes 10.2mW at 1GHz. The entire proposed All digital 90° phase-shift delay-locked loop (DLL) is designed through LT spice Software.