Implementation of radix-4 butterfly structure to prevent arithmetic overflow

The Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) play a vital role in signal processing. It is often used in many communication systems. This paper realize a 16-bit FFT architecture using radix-4 algorithm. The radix-4 structure can be used when the length of the signal is in the powers of 4. The two main challenges of this work is the complex arithmetic operations, floating point addition and multiplication operations. As we require floating point operations we went for floating point adders and multipliers. The complex multiplier is the most power consuming block in the FFT processor. The proposed Radix-4 FFT processor is realized on Verilog platform using vertex FPGA.