• DocumentCode
    3768169
  • Title

    FPGA implementation of universal asynchronous transmitter and receiver

  • Author

    Jayesh More;Rushank Suryavanshi;Gaurav Dasarwar;S Sivanantham;K Sivasankaran

  • Author_Institution
    School of Electronics Engineering, VIT University, Vellore - 632014, India
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    The proposed work in this paper describes the implementation of universal asynchronous transmitter and receiver, that is UART. The UART is a type of a serial communication protocol which serves the purpose of full duplex communication over a serial link. The UART here in is described by hardware description language that is Verilog HDL. The Verilog HDL code has been simulated in the ModelSim 10.1d and implemented on Altera DE1 board.
  • Keywords
    "Transmitters","Receivers","Clocks","Registers","Field programmable gate arrays","Generators","Hardware design languages"
  • Publisher
    ieee
  • Conference_Titel
    Green Engineering and Technologies (IC-GET), 2015 Online International Conference on
  • Type

    conf

  • DOI
    10.1109/GET.2015.7453796
  • Filename
    7453796
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3768169