• DocumentCode
    376868
  • Title

    FPGA-based DSP implementation of simple MRC beamformer

  • Author

    Kim, Minseok ; Ichige, Koichi ; Arai, Hiroyuki

  • Author_Institution
    Div. of Electr. & Comput. Eng., Yokohama Nat. Univ., Japan
  • Volume
    2
  • fYear
    2001
  • fDate
    3-6 Dec. 2001
  • Firstpage
    589
  • Abstract
    This paper describes the simple MRC (Maximal Ratio Combine) beamformer with a FPGA (Field Programmable Gate Array) for real-time signal processing and verifies its practical realization in the next generation mobile communications. FPGA is a kind of configurable CPLD (Complex Programmable Logic Device). It combines versatility of a programmable solution such as general DSP (Digital Signal Processor) with performance of dedicated hardware such as ASIC (Application Specific Integrated Circuit). It is expected that FPGA will play an important part in the various applications requiring high speed real-time processing such as DBF in the future.
  • Keywords
    adaptive antenna arrays; antenna phased arrays; array signal processing; digital signal processing chips; field programmable gate arrays; real-time systems; telecommunication computing; DBF; FPGA-based DSP implementation; MRC beamformer; adaptive array antenna technologies; digital signal processing; field programmable gate array; high speed real-time processing; maximal ratio combine beamformer; next generation mobile communications; real-time signal processing; Antenna arrays; Clocks; Digital signal processing; Directive antennas; Field programmable gate arrays; Phased arrays; Power generation; Radio frequency; Receiving antennas; Sampling methods;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microwave Conference, 2001. APMC 2001. 2001 Asia-Pacific
  • Conference_Location
    Taipei, Taiwan
  • Print_ISBN
    0-7803-7138-0
  • Type

    conf

  • DOI
    10.1109/APMC.2001.985442
  • Filename
    985442