A digital FLL and its steady-state performance analysis in Z domain

The Digital Frequency-Locked-Loop (DFLL), which is obtained usually by mapping Analog Frequency-LockedLoop (AFLL) to digital domain, is different greatly in performance from the origin AFLL, especially when loop update interval is long. To analyse DFLL´s stead-state working performance, all-phase mathematical model of a typical DFLL is established in Z domain. Analytical expressions of relation between stead-state tracking error and stability condition with loop parameters are derived. Via comparing the derived expressions of DFLL with expressions of AFLL existed in literature, several important conclusions about the difference between DFLL and AFLL are drawn. Simulation results verify the above theoretical results. The conclusion of this paper is feasible but not limited to 2-order and 3-order DFLL which are commonly used in nowadays high-dynamic receiver, the derived expressions can be used for performance evaluation, parameters optimization and loop design of DFLL.