Advanced doherty amplifier for parallel amplification

A triple-transistor Doherty power amplifier (PA) architecture supports two in-phase input and output signals is proposed in this paper. To be specific, a single carrier PA is applied to operate in the low-power region, while two peaking PAs are used in the high-power region. Compared with classic configuration which needs four transistors to realize the same functionality, the proposed design greatly reduces the overall circuit size and cost. Theoretical analysis will be given for deep understanding of the operation principle regarding this novel Doherty PA. To validate the effectiveness, a prototype PA corresponding to the proposed architecture is implemented based on Cree´s GaN HEMT transistors. Experimental results demonstrate very high drain efficiencies at both saturation and back-off regions.