A programmable error tolerant adder for image and audio processing in modern day SoCs

Modern day technology has extended its reach below 20 nm. All kinds of effects are to be seen in MOS devices due to different leakage mechanisms at deep sub-micron levels. These lead to errors in the system. Error tolerance (ET), an emerging concept in the field of VLSI design and test: by easing the restriction on accuracy, can be used to have improvements in speed and power depending on the amount of accuracy required. In this paper we propose a programmable ET adder which has the ability to control the amount of error in our design and accordingly control of power and speed and hence a use in modern day programmable (System on Chip) SoCs. We used Cadence IC design for simulating the custom made ET adder and FPGA Virtex-V for developing the prototype. The improvements can go as high as 82% in power-delay product (PDP).