A power saving cache architecture

Variable cache ways extending cache ways of mapped set to adjacent sets is proposed in literature. For w-way set associative cache, 2w ways are enabled in this architecture during address mapping. This paper proposes architecture to reduce the power consumption in this variable cache way architecture. A sequential circuit to enable occupied ways based on address mapping is introduced in level one cache adapting this algorithm. The occupied cache ways are enabled in this architecture. The unoccupied cache ways are disabled. The proposed model is simulated with SPEC2K benchmarks. An average power saving of 12% with no change in average memory access time is observed.