An enhanced erase mechanism for single poly embedded flash memory

In this paper, a mechanism using drain-floated new MOS capacitor (NCAP) is proposed to improve the erase efficiency for the single poly embedded Flash memory. By floating the source/drain junctions of PMOS and new NCAP, we observe significant increase of the gate current in negative polarity, as the generated holes cannot diffuse out but accumulated in the channel region. This feature can be used to improve the erase efficiency. However, the unstable recovery time from deep depletion makes it not practical for the single poly Flash memory. To eliminate the recovery time, a mechanism combining the new NCAP with NMOS transistor in deep n-well is proposed, which makes the drain electrode of the new NCAP biased/floated automatically. The erase efficiency can be increased up to 6 ~ 8 times as much as what it was, and the operation voltage can be lowered by about 0.6 V. Furthermore, the proposed mechanism brings only minor area overhead as each row may share one NMOS transistor in the cell array.