A high-throughput deblocking filter VLSI architecture for HEVC

This paper presents a novel VLSI hardware architecture for the real-time high-throughput implementation of the HEVC deblocking filtering. Based on the proposed implementation-friendly boundary judgment method, a dedicated multi-parallel architecture composed of four parallel filtering cores, parallel luma/chroma filtering and parallel vertical/horizontal edges filtering is presented. Experimental results demonstrate that the proposed architecture can greatly improve the performance at the expense of the slightly increased hardware cost compared to the previously known architecture in HEVC. The proposed architecture can also meet the real-time requirement of the deblocking filter for 8K×4K video format at 123fps under 278MHz clock rate.