Title :
FPGA implementation of stochastic flash A-to-D converter and its evaluation
Author :
Hisato Takehata;Toshiki Sugimoto;Hiroshi Tanimoto;Shingo Yoshizawa
Author_Institution :
Department of Electrical and Electronic Engineering, Kitami Institute of Technology, 090-8507 Japan
Abstract :
We report a hardware implementation of stochastic flash A-to-D converter (SFADC) with dynamic element matching (DEM) technique. For fast prototyping, the SFADC hardware was implemented on an FPGA board with 64 on-chip inverters using as comparators. The DEM circuit is implemented by analog multiplexer, which is put in front of the main SFADC. Measured histogram of comparator offset voltage resembles the normal distribution, but actually it is not, according to χ2 test result for 5% p-value. However, the linearization and DEM works nicely and SFDR is improved more than 5 dB by proposed SFADC with DEM, even for non-normal distribution.
Keywords :
"Field programmable gate arrays","Voltage measurement","Gaussian distribution","Standards","Hardware","Signal to noise ratio","Information and communication technology"
Conference_Titel :
Communications and Information Technologies (ISCIT), 2015 15th International Symposium on
DOI :
10.1109/ISCIT.2015.7458369