• DocumentCode
    3770893
  • Title

    Effects of array type of dummy active diffused region and gate geometries on narrow NMOSFETs with SiC S/D stressors

  • Author

    Chang-Chun Lee;Chia-Ping Hsieh;Ming-Han Liao;Sen-Wen Cheng;Yu-Huan Guo

  • Author_Institution
    Department of Mechanical Engineering, Chung Yuan Christian University, 200, Chungpei Rd., Chungli City, Taoyuan County, Taiwan 32023, R.O.C.
  • fYear
    2014
  • fDate
    7/1/2014 12:00:00 AM
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    To investigate the combined strained effects of dummy active diffused region (OD) and salient gate width of layout pattern on the mobility gain of nano-scaled device while advanced stressors of source/drain embedded silicon-carbon alloy and a tensile contact etch stop layers (CESL) are taken into account, the study uses a validated fabricated-oriented stress simulated methodology to estimate the performance of a 22nm NMOSFET.
  • Keywords
    "Logic gates","Stress","Silicon carbide","MOSFET","Metals","Layout","Silicon"
  • Publisher
    ieee
  • Conference_Titel
    Nanoelectronics Conference (INEC), 2014 IEEE International
  • Electronic_ISBN
    2159-3531
  • Type

    conf

  • DOI
    10.1109/INEC.2014.7460419
  • Filename
    7460419
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3770893