Computing embedded positive feedback loops in analog circuits using nullors

Author

Tlelo-Cuautle, E. ; Sarmiento-Reyes, L.A.

Author_Institution

Electron. Dept., INAOE, Mexico

Volume

1

fYear

2001

fDate

2001

Firstpage

53

Abstract

A partition-matrix-based method for computing embedded positive feedback loops (PFLs) in nullor-based circuits is presented. It is shown that a PFL is composed of two nullors being fully-connected. First, a modeling approach of several analog circuits using nullors is introduced. Second, a mathematical description using a canonical 2N-port representation is given. Third, a short-circuit admittance matrix having an order 2N×2N, called G_N, is computed. Finally, G_N is partitioned in N×N minors of order 2×2 from which one can compute all embedded PFLs, N being as the number of nullors

Keywords

active networks; analogue circuits; circuit feedback; electric admittance; matrix algebra; multiport networks; PFL; analog circuits; canonical 2N-port representation; embedded PFLs; embedded positive feedback loop computation; embedded positive feedback loops; fully-connected nullors; mathematical description; matrix order; matrix partitioning; modeling; nullor-based circuits; nullors; partition-matrix-based method; short-circuit admittance matrix; Admittance; Analog circuits; Analog computers; Circuit topology; Embedded computing; Feedback circuits; Feedback loop; MOSFET circuits; Network topology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on

Conference_Location

Dayton, OH

Print_ISBN

0-7803-7150-X

Type

conf

DOI

10.1109/MWSCAS.2001.986113

Filename

986113