Title :
Junctionless composite transistor for Ultra Low Power applications
Author :
Anand Kumar;Mukta Singh Parihar;Abhinav Kranti
Author_Institution :
Low Power Nanoelectronics Research Group, Electrical Engineering Discipline, Indian Institute of Technology Indore, M-Block IET-DAVV Campus, Khandwa Road, Madhya Pradesh, India
fDate :
7/1/2014 12:00:00 AM
Abstract :
In this work, we investigate the behavior of an Ultra Low Power (ULP) composite transistor in conventional inversion mode (INV) and junctionless (JL) topologies. JL ULP transistor shows enhanced on-to-off current ratio and lower leakage current at elevated temperatures. JL ULP inverter designed with composite transistor shows enhanced noise margin. The work demonstrates new opportunities for realizing future ULP circuits with junctionless transistor.
Keywords :
"Transistors","Logic gates","Leakage currents","Inverters","Nanoscale devices","Topology","Doping"
Conference_Titel :
Nanoelectronics Conference (INEC), 2014 IEEE International
Electronic_ISBN :
2159-3531
DOI :
10.1109/INEC.2014.7460447
