Resistor layout techniques for enhancing yield in ratio-critical monolithic applications

Author

Lin, Yu ; Geiger, Randall

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

Volume

1

fYear

2001

fDate

2001

Firstpage

259

Abstract

A new strategy for the layout of integrated resistors that minimizes yield loss due to random sheet resistance variations for a given area in ratio-critical applications is introduced. The strategy is based upon the optimal partitioning of area between the resistors that must be ratio-matched and on the practical realization of the partitioned resistors with unit resistor cells. This strategy provides substantial improvements in yield over what is achievable with most existing layout strategies when large and accurate resistor ratios are required

Keywords

electric resistance; integrated circuit layout; integrated circuit reliability; integrated circuit yield; thin film resistors; integrated resistors; layout strategies; layout strategy; optimal area partitioning; partitioned resistors; random sheet resistance variations; ratio-critical applications; ratio-critical monolithic applications; ratio-matched area; resistor layout techniques; resistor ratios; unit resistor cells; yield enhancement; yield improvements; yield loss; Application software; Capacitance; Capacitors; Circuits; Electric resistance; Feedback amplifiers; Resistors; Stress; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on

Conference_Location

Dayton, OH

Print_ISBN

0-7803-7150-X

Type

conf

DOI

10.1109/MWSCAS.2001.986163

Filename

986163