Title :
Induced error-correcting code for 2 bit-per-cell multi-level DRAM
Author :
Polianskikh, Boris ; Zilic, Zeljko
Author_Institution :
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada
Abstract :
Traditionally, memories employ SEC-DED (Single Error Correcting and Double Error Detecting) Error Correcting Codes (ECC). While such codes have been considered for MLDRAM (Multi-Level Dynamic Random Access Memory), their use is inefficient, due to likely double-bit errors in a single cell. For this reason we propose an induced ECC architecture that uses ECC in such a way that no common error corrupts two bits. Induced ECC allows significant increase in reliability of the MLDRAM
Keywords :
DRAM chips; error correction codes; integrated circuit reliability; memory architecture; double-bit errors; dynamic RAM reliability; dynamic random access memory; induced ECC architecture; induced error-correcting code; multi-level DRAM; Circuits; Computer architecture; Computer errors; Error correction codes; Hardware; Microelectronics; Protection; Random access memory; System-on-a-chip; Voltage;
Conference_Titel :
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-7150-X
DOI :
10.1109/MWSCAS.2001.986185
