Title :
Sequential truncated multiplication
Author_Institution :
Dept. of Electr. & Comput. Eng., Behrend Coll., Erie, PA, USA
Abstract :
The design of an N×N-bit sequential multiplier with a reduced sized accumulated partial product register is proposed. The FPGA implementation of a 24×24-bit sequential multiplier with an error less than the 24th (out of 48) bit position is shown to be 1% smaller and 13% faster than a traditional sequential multiplier
Keywords :
field programmable gate arrays; multiplying circuits; sequential circuits; 24 bit; FPGA; accumulated partial product register; bit position; sequential multiplier; sequential truncated multiplication; Computer errors; Educational institutions; Error correction; Field programmable gate arrays; Graphics; Registers; Rendering (computer graphics); Roundoff errors;
Conference_Titel :
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-7150-X
DOI :
10.1109/MWSCAS.2001.986186
