Title :
VLSI implementation of a multi-amplitude continuous phase receiver
Abstract :
A novel VLSI architecture for multi-amplitude continuous phase (MACP) receiver using CMOS technology is presented. The proposed CMOS circuit realizing the continuous phase demodulation can replace many traditional demodulation circuits in applications which require bandwidth saving and error correction capabilities since it has smaller spectral sidelobes than previous techniques. The novel receiver requires less area to be implemented, consumes less power and has less correction delay - since it uses truncated Viterbi decoder - compared to the previous realizations
Keywords :
CMOS digital integrated circuits; VLSI; Viterbi decoding; delays; demodulators; error correction; pipeline processing; CMOS technology; VLSI implementation; area; bandwidth saving; continuous phase demodulation; correction delay; error correction capabilities; multi-amplitude continuous phase receiver; spectral sidelobes; truncated Viterbi decoder; CMOS technology; Counting circuits; Decoding; Delay; Demodulation; Error correction; Operational amplifiers; Signal generators; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-7150-X
DOI :
10.1109/MWSCAS.2001.986195