DocumentCode :
37717
Title :
A Polynomial Time Exact Algorithm for Overlay-Resistant Self-Aligned Double Patterning (SADP) Layout Decomposition
Author :
Zigang Xiao ; Yuelin Du ; Hongbo Zhang ; Wong, Martin D. F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Volume :
32
Issue :
8
fYear :
2013
fDate :
Aug. 2013
Firstpage :
1228
Lastpage :
1239
Abstract :
Double patterning lithography (DPL) technologies have become a must for today´s sub-32 nm technology nodes. Currently, there are two leading DPL technologies: self-aligned double patterning (SADP) and litho-etch-litho-etch (LELE). Among them, SADP has the significant advantage over LELE in its ability to avoid overlay, making it the likely DPL candidate for the next technology node of 14 nm. In any DPL technology, layout decomposition is the key problem. While the layout decomposition problem for LELE has been well studied in the literature, only a few attempts have been made to address the SADP layout decomposition problem. In this paper, we present a polynomial time exact (optimal) algorithm to determine if a given layout has SADP decompositions that do not have any overlay at specified critical edges. The previous approaches tried to minimize the total overlay of a given layout, which may be a problematic objective. Furthermore, all previous exact algorithms were computationally expensive exponential time algorithms based on SAT or ILP. Other previous algorithms for the problem were heuristics without having any guarantee that an overlay-free solution can be found even if one exists.
Keywords :
computational complexity; etching; lithography; DPL technologies; LELE; SADP; double patterning lithography; layout decomposition; litho-etch-litho-etch; overlay-free solution; overlay-resistant self-aligned double patterning; polynomial time exact algorithm; Algorithm design and analysis; Color; Layout; Merging; Polynomials; Printing; Shape; Computer-aided design; design for manufacturability; electronic design automation; layout decomposition; polynomial time algorithm; self-aligned double patterning;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2013.2252054
Filename :
6558884
Link To Document :
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