The Optimized Implementation of Affine Transformation of S-Box in Rijndael Algorithm

Rijndael algorithm as AES has been implemented by hardware recently to improve the performance such as RFID-tag. Based on the research of S-box structure principle, this paper firstly analyzes the problem of short iterative output period and then presents novel hardware architecture of affine transformation based on improved polynomials. The architecture is simulated in Verilog HDL and implemented in FPGA designs. Compared with traditional circuits, the presented architecture further simplifies the operation process and reduces the S-box. Compared with traditional circuits, the presented hardware size is only 75 gates and the optimal ratio reaches 90.23% and even 47.92%.