Application of logical effort on design of arithmetic blocks

Author

Yu, Xiao Yan ; Oklobdzija, Vojin G. ; Walker, William W.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

Volume

1

fYear

2001

fDate

4-7 Nov. 2001

Firstpage

872

Abstract

In this paper, we review the logical effort model presented in Sutherland et al. (1991). Based on the HSPICE simulation results using 0.18 /spl mu/m CMOS technology as applied to logic blocks used in arithmetic circuits; we analyze the efficiency of the model and also present modifications that include modeling of wire delay. We propose a new model for logical effort that better fits the behavior of these blocks. The results are applicable for evaluation of arithmetic units as well as for development of new arithmetic algorithms. Our ultimate objective is to close the gap between arithmetic algorithms and their performance in VLSI CMOS.

Keywords

CMOS logic circuits; SPICE; VLSI; adders; delay estimation; digital arithmetic; 0.18 micron; CMOS circuits; HSPICE simulation; VLSI; arithmetic circuits; logic blocks; logical effort model; performance; wire delay modeling; Analytical models; Arithmetic; CMOS logic circuits; CMOS technology; Circuit analysis; Circuit simulation; Delay; Semiconductor device modeling; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-7147-X

Type

conf

DOI

10.1109/ACSSC.2001.987048

Filename

987048