Design of compact and low power reversible comparator

According to the Launder´s principle, in binary for each bit loss information kTln2 of heat is dissipated. All the present designs like CMOS are irreversible logics which losses bit information. Reversible logic is the better way of reducing power consumption. Bit loss always give the more power consumption but here by recovering bit loss using reversible logic we are getting less power consumption, as well as less number of gates and high speed. In this paper, we proposed a reversible n-bit binary comparator, the calculation for quantum cost, number of gates, garbage outputs, power, delay and algorithm for constructing is presented. In this paper we got the improvement of 37.5% for number of gates, 43.5% for power consumption and 44.22% for delay of 4 bit comparator over conventional.