Novelty in architecture of ROBDD for the minimization of interconnect delay

In VLSI design of system configuration, three parameters are of major important. Among these three parameters speed, area and power the speed is dependent on the delay of the system. In high speed system design the design delay is contributed by interconnect delay which is the connecting delay of various modules (nodes) i.e. Integrated Protocol. Because of scaling down in the design of high speed system, it is essential to concentrate more towards interconnect delay of the system design to get the optimized delay. Two- level and Multi-level logic minimization is a major problem in logic synthesis and also has the application in modeling in the stages of placement and routing, in fault modeling and in verification of combinational and sequential circuits. Binary Decision Diagram (BDD) is a well-known and widely used in logic synthesis and formal verification of integrated circuits. In this paper various structures of Binary Decision Diagram was studied and experimented to justify the reduction in interconnect delay.