Noise tolerant current mirror footed domino logic

As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the input of domino logic. Domino logic circuit has two stages first is dynamic logic part which is followed by a static inverter. This static inverter consumes very less power and has high noise immunity. In this paper a novel circuit called current mirror footed domino logic has been proposed for CMOS domino logic. This proposed domino logic is noise tolerant and has low power consumption than the basic footed and footless domino logic styles. Unity noise gain (UNG) found is also good for this logic style as compared to the previous proposed logic styles.