Area power and speed optimized serial type daisy chain memory using modified CPG with SSASPL

A low power area reduced and speed improved serial type daisy chain memory register also known as shift Register is proposed by using modified clock generator circuit and SSASPL (Static differential Sense Amplifier based Shared Pulsed Latch). This latch based shift register consumes low area and low power than other latches. There is a modified complementary pass logic based 4 bit clock pulse generator with low power and low area is proposed that generates small clock pulses with small pulse width. These pulses are given to the conventional shift register that results high speed. The system is designed by the Cadence virtuoso 180 nm technology. The Maximum supply voltage for the system, clock source and input source are 1.8V. The complementary pass logic based proposed system reduces the area about 7% for the total system and about 23% for the 4 bit clock pulse generator circuit. The Power is reduced by 26% than the conventional system. The speed is improved about 7% than the existing system.