Survey over on-chip buses for VLSI Architecture with optimized delay for multiprocessor system design

In VLSI system design speed, area, and power are the three parameters playing a vital role. Among them the speed is purely determined by the delay taken by the design for its processing. In the delay, the design delay is mainly decided by gate delay. Nowadays in the design, the path or routing delay dominates more towards the design delay compare to the earlier days where gate delay dominates more towards the design delay. Because of scaling down in the design, it is essential to concentrate more towards routing delay of the design to get the optimized delay or desired speed of the design. In this paper, various on chip buses used for VLSI Architecture for multi processor system design were surveyed in intention with delay optimization towards system design.