DocumentCode
3774962
Title
The Cavium 32 Core OCTEON II 68xx
Author
R. E. Kessler
Author_Institution
Cavium, Inc. Hot Chips 23 August, 2011
fYear
2011
Firstpage
1
Lastpage
33
Abstract
Presents a collection of slides covering the following topics: Cavium 32 core OCTEON II 68xx; power scalability; cache coherence; interconnect bandwidth; memory bandwidth; chip floorplan; hardware work queueing; scheduling; synchronization; ordering assist; and coprocessor acceleration.
Keywords
"Scalability","Program processors","Wireless LAN","Hardware"
Publisher
ieee
Conference_Titel
Hot Chips 23 Symposium (HCS), 2011 IEEE
Type
conf
DOI
10.1109/HOTCHIPS.2011.7477487
Filename
7477487
Link To Document