DocumentCode :
3775025
Title :
A novel processor architecture for high-performance stream processing
Author :
Jan van Lunteren
Author_Institution :
IBM Research GmbH, Zurich Research Laboratory, S?umerstrasse 4, CH-8803 R?schlikon, Switzerland
fYear :
2006
Firstpage :
1
Lastpage :
24
Abstract :
This article consists of a collection of slides from the author´s conference presentation on a novel processor architecture for high performance stream processing. Some of the specific topics discussed include: an introduction to the technology and applications supported; high-level concept design; programmable state machine; novel processor technologies; instructure cache ad prefetch; and experimental results for testing the performance output.
Keywords :
"Prefetching","Coprocessors","Program processors","XML","Pattern matching","Encryption","Programmable state machines"
Publisher :
ieee
Conference_Titel :
Hot Chips 18 Symposium (HCS), 2006 IEEE
Type :
conf
DOI :
10.1109/HOTCHIPS.2006.7477868
Filename :
7477868
Link To Document :
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