FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture

Field-Programmable Gate Arrays (FPGAs) have turned out to be a well-liked target for implementing cryptographic block ciphers. In this research work, recently proposed 64 bit Secure Force (SF) algorithm is implemented on an FPGA based full loop-unroll architecture. The proposed FPGA implementation of Secure Force yields a throughput of 2.3 Gbps for encryption, 2.6 Gbps for decryption, and 3.43 Gbps for key expansion at the cost of as low as 476, 400, and 160 slices for encryption, decryption, and key expansion respectively. The results obtained after extensive testing indicate that the throughput per unit area (throughput/slice) for the proposed implementation is comparable with many FPGA implementations of AES algorithm. The proposed design consumes 117.18 milli Watts thermal power.