DocumentCode :
3776184
Title :
Hybrid multiplier for ECC
Author :
Ravi Kishore Kodali;Siva Kumar;Vishal Jain;Boppana Lakshmi
Author_Institution :
Department of Electronics and Communication Engineering, National Institute of Technology, Warangal, WARANGAL, 506004
fYear :
2015
Firstpage :
65
Lastpage :
70
Abstract :
The quest for faster and power efficient algorithms has necessiated the need for faster and power efficient multipliers since multiplication is used frequently. Often, the numbers to be multiplied are quite large. The multiplication method proposed in this work, Nikhilam sutra or algorithm, is derived from the ancient Indian texts known as Vedas. Elliptic curve cryptography (ECC) involves repeated application of multiplication of higher size numbers. This work combines two vedic sutras, Nikhilam, Urdhva tirakbhyam along with Karatsuba algorithms to form unique multiplier to carry out multiplication of large unsigned binary numbers. The multiplier has been implemented for two different data sets using Xilinx Virtex-6, 6vlx760ff1760-2 FPGA device. The Nikhilam, Karatsuba and Urdhva tirakbhyam algorithms are compared in terms of time delay, resources utilized and power consumption. The results are tabulated for two key lengths, 194-bits and 233-bits as needed in ECC.
Keywords :
"Signal processing algorithms","Field programmable gate arrays","Delay effects","Elliptic curve cryptography","Hardware","Time complexity","Mathematical model"
Publisher :
ieee
Conference_Titel :
Intelligent Computational Systems (RAICS), 2015 IEEE Recent Advances in
Type :
conf
DOI :
10.1109/RAICS.2015.7488390
Filename :
7488390
Link To Document :
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