Adiabatic technique for fat tree decoder to be used in flash ADCs

Today power dissipation is the most critical problem in Low Power circuits in VLSI design. Adiabatic technique is a technique to reduce power dissipation in digital circuits in which energy stored in a capacitor can be recycled rather than dissipated as heat. In this paper the Fat tree decoder incorporating PFAL i.e. Positive Feedback Adiabatic Logic technique has been simulated using SPICE simulation tool and its power dissipation has been calculated. In this technique, the energy is recovered during recovery phase of the clock supply. The PFAL based decoder has shown a decrease of 50% in the power dissipation as compared to conventional CMOS based decoder within a specific practical range of frequency. Such a low power decoder can be very useful for further use in highly complex designs of A to D and D to A converters.