Real-time parallel implementation of road traffic radar video processing algorithms on a parallel architecture based on DSP and ARM processors

Machine vision algorithms require high-computing power. A high performance parallel system has been proposed in this paper by implementing a road traffic radar video processing chain in real-time on a new embedded architecture. The proposed machine consists of the Digital Signal Processor (DSP) 66AK2H12 from Texas Instruments (TI). The goal of this paper is the estimation of the vehicles number, speeds and classification through an optimal exploitation of the parallel architecture based on DSP and ARM cores and high speed buses used in the video acquisition and processing.