Tackling SoC abstraction gap: Raising the abstraction level of DUT verification

To meet the ever increasing demand of consumer electronics industry, the complexity of System on Chip has increased rapidly and thus, in the past few years efforts are being made to reuse IPs at different abstraction levels from different vendors designed using various hardware description languages. Complex IPs, with different data Payload Structures and Models of Computation, are integrated in SoC making it difficult to trace the simulation issues of Design Under Test, i.e. DUT at system level. To address this issue, TLM 2.0 suggests modeling the System on Chip at higher abstraction level. TLM 2.0 advocates the usage of TLM models as Golden Reference for RTL SoC. The TLM Model of the DUT developed as a part of TLM test bench can be conveniently used at system level for analyzing simulation issues related to RTL DUT but comparing and subsequently analyzing the simulation results of TLM and RTL test benches is a cumbersome task and has yet not standardized. Thus, almost all the Electronics System Level users are devising customized methodologies convenient to them for comparing the simulation results of TLM and RTL test benches. In this work, a novel approach is proposed to list the discrepancy between the TLM and RTL test benches and compute the divergence percentage for functional verification of DUT. No emphasis is given to the information held in internal structure of DUT and only functional aspect of DUT is taken into consideration. Selective parameters of Transaction Payload are thus, conveniently compared during the simulation time across the various abstraction levels to find out the ambiguous behavior of DUT. Based on empirical results, we argue that the annotations proposed causes reasonable overhead, but provide convenient approach for functional verification of complex DUT.