Title :
An 8-bit 35-MS/s successive approximation register ADC
Author :
Xiucheng Zhou; Ying Zhang; Yun Su
Author_Institution :
College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications, China
Abstract :
An 8-bit 35-MS/s successive approximation register analog-to-digital converter implemented in 0.18μm CMOS process is presented in this paper. To reduce the total power consumption, split capacitor DAC structure coupled with Merged Capacitor Switching (MCS) technique is used. In addition, dynamic comparator without pre-amplifier is applied to improve the energy efficiency. With the supply voltage of 1.8V and sampling rate of 35-MS/s, the ADC consumes 0.65mw and achieves an effective number of bits (ENOB) of 7.15 bits.
Keywords :
"Capacitors","Switches","CMOS integrated circuits","MATLAB"
Conference_Titel :
Progress in Informatics and Computing (PIC), 2015 IEEE International Conference on
Print_ISBN :
978-1-4673-8086-7
DOI :
10.1109/PIC.2015.7489904
