Detection and identification of logic gates from document images using mathematical morphology

Decomposition and representation of digital logic circuit drawings to a suitable vector form has widespread applications related to data compression, storage, analysis, and editing. In this paper, we propose an efficient method for segmenting and identifying logic gate symbols from the image of a circuit drawing. The segmentation procedure is based on morphological operations. After segmentation, the symbols are identified by a decision tree classifier. The proposed method may be used for vectorization of circuit drawings utilizing the information on the segmented circuit symbols and their connectivity matrices. We have tested the proposed method on a dataset containing 53 scanned images of a variety of digital logic circuit drawings. Some of the results are presented here to demonstrate its efficiency.