A configurable management strategy for parallel access of coarse-grained reconfigurable architecture for radar processing

In order to reduce the date access conflicts and improve the memory access efficiency in radar signal processing, a linear varying step-size data management strategy combined with a hierarchical memory structure is proposed. By proposing the logical mapping strategy between the reconfigurable arrays and the multi-bank memory, the memory access performance of reconfigurable processor is improved and the reconfigurable system achieves higher throughput. Simulated on the SMIC 40nm CMOS technology, the experimental results show that the memory access performance can be improved by nearly 35%, in comparison to the representative PMA at a 500MHz operating frequency. For example, the access performance of 256-point to 64k-point FFT can be improved by 26.09% to 54.60%.