Title :
Speed-independent floating point coprocessor
Author :
Y. A. Stepchenkov;V. N. Zakharov;Y. V. Rogdestvenski;Y. G. Diachenko;N. V. Morozov;D. Y. Stepchenkov
Author_Institution :
Department of perspective computer systems architecture, Institute of Informatics Problems, Federal Research Center ?Computer Science and Control? of the Russian Academy of Sciences (IPIFRC CSC RAS), IPI RAS, Moscow, Russian Federation
Abstract :
Speed-independent fused multiply-add unit as a coprocessor is represented. It purely conforms to IEEE 754 Standard. For minimization hardware and power consumption, a number of pipeline stages is reduced down to two. Wallace tree in the multiplier utilizes redundant self-timed code. Represented unit is developed on a base of standard 65-nm CMOS bulk process. It provides a performance up to 0.54 Gflops, and power consumption at level of 450 m W/Gflops.
Keywords :
"Pipelines","Registers","Power demand","Hardware","Standards","Encoding","Coprocessors"
Conference_Titel :
East-West Design & Test Symposium (EWDTS), 2015 IEEE
DOI :
10.1109/EWDTS.2015.7493110
