Automatic transformation of SystemC designs to speed up simulation

SystemC language is widely used for hardware design and verification. Simulation of large SystemC designs may be quite time-consuming, that limits its applicability, especially in virtual platforms. In this paper we propose an approach to speed up simulation of synthesizable SystemC designs. The approach is based on automatic transformation of the design to equivalent one with event-based synchronization, which simulation is much faster. Our approach is implemented in the SCAccel tool and a SystemC kernel patch, which are available to download. The evaluation results for a real world system-on-chip show performance boost 1.6...41 times, depends on testbench and system configuration.