Modeling transistor level masking of soft errors in combinational circuits

Technology scaling in modern electronic circuits shrinks the transistor size and dramatically increases the sensitivity of semiconductor devices to radiations. Consequently, soft errors emerged as a serious reliability threat in both sequential and combinational circuits. To accurately estimate Soft Error Rates (SERs) within combinational circuits, the impact of masking mechanisms should be considered and precisely modeled. In fact, overestimating SERs may lead to unnecessary hardware resources overhead as well as higher power consumption and circuit complexity. This paper examines the effect of logic gates architecture on the SERs in CMOS logic circuits. We consider the impact of the Transistor Level Masking (TLM) and propose a probabilistic model for both circuit and gate levels The experimentations show that the probability of soft error masking due to TLM mechanism can reach 100% for NAND gates, 45% for c17 ISCAS´85 benchmark and 47% for a simplified c6288 ISCAS´85 benchmark.