• DocumentCode
    3777810
  • Title

    Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor

  • Author

    Vazgen Melikyan;Eduard Babayan;Anush Melikyan;Davit Babayan;Poghos Petrosyan;Edvard Mkrtchyan

  • Author_Institution
    National polytechnic university of Armenia, Synopsys Armenia CJSC
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper presents method of power optimization implemented on RISC architecture ORCA processor with the help of clock gating and multi-threshold approach aimed at significant reduction of dynamic (switching) power and leakage power. The results are compared with previous research implementing other low power technique on the same processor and with standard design.
  • Keywords
    "Clocks","Reduced instruction set computing","Design methodology","Standards","Power demand","Timing","Registers"
  • Publisher
    ieee
  • Conference_Titel
    East-West Design & Test Symposium (EWDTS), 2015 IEEE
  • Type

    conf

  • DOI
    10.1109/EWDTS.2015.7493159
  • Filename
    7493159
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3777810